Defines | |
| #define | CARD_SPI_ENABLE_BIT (1 << 15) |
| #define | CARD_SPI_IRQ_BIT (1 << 14) |
| #define | CARD_SPI_SLOT_CS_BIT (1 << 13) |
| #define | CARD_SPI_BUSY_BIT (1 << 7) |
| #define | CARD_SPI_CS_HOLD_BIT (1 << 6) |
| #define | CARD_SPI_BUSY_TEST (CARD_CR1 & CARD_SPI_BUSY_BIT) |
| #define | CARD_SPI_WAIT_IDLE() while ( CARD_SPI_BUSY_TEST); |
| #define CARD_SPI_BUSY_BIT (1 << 7) |
The busy bit in the control register (0 idle, 1 busy)
| #define CARD_SPI_BUSY_TEST (CARD_CR1 & CARD_SPI_BUSY_BIT) |
Test if the SPI bus is busy (0 is idle, non-zero busy)
| #define CARD_SPI_CS_HOLD_BIT (1 << 6) |
The Chip Select Hold bit
| #define CARD_SPI_ENABLE_BIT (1 << 15) |
Enable the SPI controller
| #define CARD_SPI_IRQ_BIT (1 << 14) |
Generate an interrupt request when the transfer is complete
| #define CARD_SPI_SLOT_CS_BIT (1 << 13) |
The Chip Select signal for the DS Slot
| #define CARD_SPI_WAIT_IDLE | ( | ) | while ( CARD_SPI_BUSY_TEST); |
Wait for the SPI bus to become idle
1.4.7